| JPEG Encoder Features This IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Compressor / Encoder. Its main features are: * Baseline DCT compression according to JPEG ITU-T T.81 | ISO/IEC 10918-1 standard. * JFIF 1.02 standard file header. * Drag'n'drop IP block for Xilinx Vivado Block Design and Altera Quartus Qsys. * Constant throughput: 16 compressed pixels every 3 clock cycles: 5.3 pixels/cycle color and 8 pixels/cycle grayscale * Industry standard interfaces: AXI-Lite slave for configuration/status and AXI3/4 master for pixel-input/encoded-output. * Embedded DMA engines in AXI3/4 interfaces for direct connection to a memory controller. Support for high latency memories. * On-the-fly selectable quality level/compression ratio from 1 to 100 before every compression. * Selectable JPG chroma subsampling (4:4:4, 4:2:2, 4:2:0), independent of input subsampling. * Unlimited image resolution (up to 64K x 64K as per JPEG spec.). * Support for RGB and YCbCr input pixels' color space support. * Unlimited Restart markers support. * ASIC: On ASIC TSMC 0.13G process technology over 166 Mpix/s (>250 MHz) Throughput This IP core is available in 4 different speeds: 1x, 2x, 4x, and 8x. Each with a different relative size and licensing. The pixel throughputs are:  Download Xilinx Vivado component https://www.visengi.com/docs/VISENGI_JPEGE_Xilinx.zip Download Altera Qsys component https://www.visengi.com/docs/VISENGI_JPEGE_Altera.zip More information, please refer to the following website https://www.visengi.com/products/jpeg_hardware_encoder 詳細資料與需求請洽詢 哲想方案有限公司 (Cogito Solutions Ltd) www.cogitosolutions.com 查詢 e-mail: salestw@cogitosolutions.com 電話: 02-2722-3381 |
